The present invention relates to copper (Cu) and/or Cu alloy metallization in semiconductor devices, particularly to a method for forming reliable Cu or Cu alloy interconnects, such as single and dual damascene structures in low dielectric constant materials. The present invention is particularly applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnects with improved electromigration resistance.
The escalating demand for high density and performance impose severe requirements on semiconductor fabrication technology, particularly interconnection technology in terms of providing a low Rxc3x97C (resistancexc3x97capacitance) interconnect pattern with electromigration resistance wherein submicron vias, contacts and trenches have high aspect ratios. Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed interlayer dielectrics and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising five or more levels of metallization are becoming more prevalent as device geometry""s shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an interlayer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening through the interlayer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interlayer dielectric is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the interlayer dielectric and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the Rxc3x97C delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.12 micron and below, the rejection rate due to integrated circuit speed delays significantly reduces production throughput and increases manufacturing costs. Moreover, as line widths decrease electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in interconnect metallizations. Cu is relatively inexpensive, easy to process, and has a lower resistively than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP. However, due to Cu diffusion through interdielectric layer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Tixe2x80x94TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional interconnect methodology. For example, as the feature size is reduced into the deep submicron range, the aspect ratio increases and voids are typically generated in the interconnects. Adverting to FIG. 1, an underlying feature, e.g., a metal line, is formed in dielectric layer 10 with a capping layer 12 thereon. Overlying dielectric layers 13 and 15 are formed with an intervening etch stop layer 14. A dual damascene structure is formed by etching an opening in dielectric layers 13 and 15, depositing a barrier metal layer 16, depositing Cu or a Cu alloy to fill the opening, and conducting CMP to form Cu line 17A in communication with underlying Cu via 17B electrically connected to underlying metal feature 11. A silicon nitride capping layer 18 is then deposited. Voids 19 are typically formed which adversely impact circuit reliability and decrease electromigration resistance. Such voids may stem from various sources, such as the manifest difficulty in completely filling openings having a reduced size, such as a via opening of about 0.21 to about 0.23 micron.
As design rules extend deeper into the submicron range, the reliability of interconnect patterns becomes particularly critical and electromigration becomes increasingly problematic. Accordingly, there exists a continuing need for methodology enabling the formation of encapsulated Cu and Cu alloy interconnects for vertical metallization levels with greater accuracy, improved reliability, increased electromigration resistance and reduced contact resistance. There exists a particular continuing need for methodology enabling the formation of Cu or Cu alloy dual damascene structures formed in dielectric material having a low dielectric constant (k), with improved reliability and electromigration resistance and reduced contact resistance.
An advantage of the present invention is a method of manufacturing a semiconductor device having highly reliable Cu or Cu alloy interconnects with improved electromigration resistance and reduced contact resistance.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming an opening in a dielectric layer; depositing Cu or a Cu alloy to fill the opening; and laser thermal annealing the deposited Cu or Cu alloy in ammonia (NH3).
Embodiments of the present invention comprise laser thermal annealing by impinging a pulsed laser light beam on the deposited Cu or Cu alloy at a radiant fluence of about 0.28 to about 0.34 joules/cm2, employing an NH3 flow rate of about 200 to about 2,000 sccm, to elevate the temperature of the deposited Cu or Cu alloy to about 983xc2x0 C. to about 1183xc2x0 C., thereby reflowing the deposited Cu or Cu alloy and eliminating voids. The use of NH3 during laser thermal annealing advantageously reduces copper oxide prior to and during reflowing, thereby decreasing contact resistance and improving device reliability.
Embodiments of the present invention include planarizing by conducting CMP subsequent to laser thermal annealing leaving an exposed Cu or Cu alloy surface substantially co-planar with the upper surface of the dielectric layer, treating the exposed Cu or Cu alloy surface in a plasma containing NH3 to remove copper oxide therefrom and then depositing a silicon nitride capping layer by plasma enhanced chemical vapor deposition (PECVD) on the plasma treated surface.
Embodiments of the present invention further include single and dual damascene techniques comprising forming an opening in one or more interlayer dielectrics on a wafer, depositing an underlying diffusion barrier layer, such as a composite comprising a tantalum nitride layer lining the opening and a layer of alpha-tantalum (xcex1-Ta) on the tantalum nitride layer. A seedlayer can then be deposited. A Cu or a Cu alloy layer is then deposited filling the opening. Laser thermal annealing in NH3 is then conducted to reduce copper oxide and reflow the deposited Cu or Cu alloy to eliminate voids. CMP is then conducted to remove the Cu or Cu alloy layer beyond the opening leaving an exposed surface oxidized. The wafer is then conveyed into a chamber wherein the exposed surface of the Cu or Cu alloy layer is treated with a plasma in NH3 to remove any copper oxide formed during CMP. Silane (SiH4) is then introduced and a silicon nitride capping layer is deposited on the plasma treated surface by PECVD.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.